Scaling of device dimensions has been a primary factor driving improvements in integrated circuit performance and reduction in integrated circuit cost. Due to limitations associated with existing gate-oxide thicknesses and source/drain (S/D) junction depths, scaling of existing bulk metal oxide semiconductor field effect transistor (MOSFET) devices below the 0.1 μm process generation may be difficult, if not impossible. New device structures and new materials, thus, are likely to be needed to improve FET performance.
Double-gate MOSFETs represent new devices that are candidates for succeeding existing planar MOSFETs. A FinFET is a recent double-gate structure that includes a channel formed in a vertical fin. The FinFET is similar to existing planar MOSFETs in layout and fabrication. The FinFET also provides a range of channel lengths, CMOS compatibility and large packing density compared to other double-gate structures.
Fins of existing FinFETs are conventionally formed by direct etching of the layer of material that is to form the fin channel. This conventional direct etching can lead to rough fin sidewalls and, possibly, damage to the fin sidewalls. Such roughness and/or damage can negatively impact the performance of the eventual constructed FinFET. Therefore, there exists a need for methods for forming a fin of a FinFET that avoids the use of direct etching.